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8.  Direct Memory Access (DMA) DMA Operations DMA Attributes  Previous   Contents   Next 
   
 

ddi_dma_attr Structure

The DMA attribute structure has the following members:

typedef struct ddi_dma_attr {
        uint_t          dma_attr_version;       /* version number */
        uint64_t        dma_attr_addr_lo;       /* low DMA address range */
        uint64_t        dma_attr_addr_hi;       /* high DMA address range */
        uint64_t        dma_attr_count_max;     /* DMA counter register */
        uint64_t        dma_attr_align;         /* DMA address alignment */
        uint_t          dma_attr_burstsizes;    /* DMA burstsizes */
        uint32_t        dma_attr_minxfer;       /* min effective DMA size */
        uint64_t        dma_attr_maxxfer;       /* max DMA xfer size */
        uint64_t        dma_attr_seg;           /* segment boundary */
        int             dma_attr_sgllen;        /* s/g length */
        uint32_t        dma_attr_granular;      /* granularity of device */
        uint_t          dma_attr_flags;         /* Bus specific DMA flags */
} ddi_dma_attr_t;
dma_attr_version

Version number of the attribute structure. It should be set to DMA_ATTR_V0.

dma_attr_addr_lo

Lowest bus address that the DMA engine can access.

dma_attr_addr_hi

Highest bus address that the DMA engine can access.

dma_attr_count_max

Specifies the maximum transfer count that the DMA engine can handle in one cookie. The limit is expressed as the maximum count minus one. It is used as a bit mask, so it must also be one less than a power of two.

dma_attr_align

Specifies additional alignment requirements for any allocated DMA resources. This field can be used to force more restrictive alignment than implicitly specified by other DMA attributes, such as alignment on a page boundary.

dam_attr_burstsizes

Specifies the burst sizes that the device supports. (A burst size is the amount of data the device can transfer before relinquishing the bus.) This member is a binary encoding of burst sizes, assumed to be powers of two. For example, if the device is capable of doing 1-, 2-, 4-, and 16-byte bursts, this field should be set to 0 x 17. The system also uses this field to determine alignment restrictions.

dma_attr_minxfer

Minimum effective transfer size the device can perform. It also influences alignment and padding restrictions.

dma_attr_maxxfer

Describes the maximum number of bytes that the DMA engine can transmit or receive in one I/O command. This limitation is only significant if it is less than (dma_attr_count_max + 1) * dma_attr_sgllen.

dma_attr_seg

Upper bound of the DMA engine's address register. This is often used where the upper 8 bits of an address register are a latch containing a segment number, and the lower 24 bits are used to address a segment. In this case, dma_attr_seg would be set to 0xFFFFFF, which prevents the system from crossing a 24-bit segment boundary when allocating resources for the object.

dma_attr_sgllen

Specifies the maximum number of entries in the scatter-gather list. It is the number of cookies that the DMA engine can consume in one I/O request to the device. If the DMA engine has no scatter-gather list, this field should be set to one.

dma_attr_granular

This field describes the granularity of the device's DMA transfer ability, in units of bytes. This value is used to specify, for example, the sector size of a mass storage device. DMA requests will be broken into multiples of this value. If there is no scatter-gather capability, then the size of each DMA transfer will be a multiple of this value. If there is scatter-gather capability, then a single segment will not be smaller than the minimum transfer value, but can be less than the granularity; however the total transfer length of the scatter-gather list will be a multiple of the granularity value.

dma_attr_flags

This field can be set to DDI_DMA_FORCE_PHYSICAL, which indicates that the system should return physical rather than virtual I/O addresses if the system supports both. If the system does not support physical DMA, the return value from ddi_dma_alloc_handle(9F) will be DDI_DMA_BADATTR. In this case, the driver has to clear DDI_DMA_FORCE_PHYSICAL and retry the operation.

SBus Example

A DMA engine on an SBus in a SPARC machine has the following attributes:

  • It can access only addresses ranging from 0xFF000000 to 0xFFFFFFFF.

  • It has a 32-bit DMA counter register.

  • It can handle byte-aligned transfers.

  • It supports 1-, 2- and 4-byte burst sizes.

  • It has a minimum effective transfer size of 1 byte.

  • It has a 32-bit address register.

  • It doesn't have a scatter-gather list.

  • The device operates on sectors only (for example a disk).

The resulting attribute structure is:

static ddi_dma_attr_t attributes = {
    DMA_ATTR_V0,      /* Version number */
    0xFF000000,       /* low address */
    0xFFFFFFFF,       /* high address */
    0xFFFFFFFF,       /* counter register max */
    1,                /* byte alignment */
    0x7,              /* burst sizes: 0x1 | 0x2 | 0x4 */
    0x1,              /* minimum transfer size */
    0xFFFFFFFF,       /* max xfer size */
    0xFFFFFFFF,       /* address register max */
    1,                /* no scatter-gather */
    512,              /* device operates on sectors */
    0,                /* attr flag: set to 0 */
};

ISA Bus Example

A DMA engine on an ISA bus in an IA machine has the following attributes:

  • It accesses only the first 16 megabytes of memory.

  • It cannot cross a 1 megabyte boundary in a single DMA transfer.

  • It has a 16-bit counter register.

  • It can handle byte-aligned transfers.

  • It supports 1-, 2- and 4-byte burst sizes.

  • It has a minimum effective transfer size of 1 byte.

  • It can hold up to 17 scatter-gather transfers.

  • The device operates on sectors only (for example a disk).

The resulting attribute structure is:

static ddi_dma_attr_t attributes = {
    DMA_ATTR_V0,      /* Version number */
    0x00000000,       /* low address */
    0x00FFFFFF,       /* high address */
    0xFFFF,           /* counter register max */
    1,                /* byte alignment */
    0x7,              /* burst sizes */
    0x1,              /* minimum transfer size */
    0xFFFFFFFF,       /* max xfer size */
    0x000FFFFF,       /* address register max */
    17,               /* scatter-gather */
    512,              /* device operates on sectors */
    0,                /* attr flag: set to 0 */
};
 
 
 
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