Document fins/I0925-1
FIN #: I0925-1
SYNOPSIS: Flashupdating the LPOST image on a System Board does not require the
domain to be down
DATE: Jan/16/03
KEYWORDS: Flashupdating the LPOST image on a System Board does not require the
domain to be down
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- Sun Proprietary/Confidential: Internal Use Only -
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FIELD INFORMATION NOTICE
(For Authorized Distribution by SunService)
SYNOPSIS: Flashupdating the LPOST image on a System Board does not
require the domain to be down.
SunAlert: No
TOP FIN/FCO REPORT: No
PRODUCT_REFERENCE: Sun Fire 15K/12K
PRODUCT CATEGORY: Server / Service
PRODUCTS AFFECTED:
Systems Affected:
-----------------
Mkt_ID Platform Model Description Serial Number
------ -------- ----- ----------- -------------
- F12K ALL Sun Fire 12000 -
- F15K ALL Sun Fire 15000 -
X-Options Affected:
-------------------
Mkt_ID Platform Model Description Serial Number
------ -------- ----- ----------- -------------
- - - - -
PART NUMBERS AFFECTED:
Part Number Description Model
----------- ----------- -----
- - -
REFERENCES:
URL: http://pts-americas.west/esg/hsg/starcat/xctt/sms_firmware.html
PROBLEM DESCRIPTION:
Updating the LPOST image on Sun Fire 12K/15K System Boards does not
require that domains be brought down. Following the LPOST update
procedures provided in this FIN will allow field personnel to update
firmware in a more timely manner and will prevent unnecessary downtime
for customer domains.
This issue affects any Sun Fire 12K/15K domain which requires an LPOST
image update. This can be necessary when a firmware patch is installed
on the System Controller (SC) to provide a bug fix, requiring the
System Boards in a domain to be updated. This may also be needed when
a System Board FRU containing uprev/downrev firmware is installed into a
domain. This may require a flashupdate, as all System Boards in a
domain should contain the same LPOST version.
The current LPOST level flashed on the CPU/MCPU boards and the LPOST
level in the SC disk image can be displayed using the 'flashupdate'
command:
%'flashupdate -d X -f /opt/SUNWSMS/hostobjs/sgcpu.flash -n
(where X is the letter [A-R] of the domain)
The POST process will report any discrepancy in LPOST versions as shown
by either of the messages below:
1) sgcpu.flash file: NOTE: lpost_vercheck(): Using up-rev LPOST
version 5.13.1 Build 2.0 I/F 12 (from: 5.13.0 Build 0 I/F 12)
Fprom SB0/F0: NOTE: lpost_vercheck(): Using up-rev LPOST version
5.13.1 Build 2.0 I/F 12 (from: 5.13.0 Build 0 I/F 12)
2) NOTE: Mixed Minor numbers: 4
All LPOSTs in a domain should use the same version.
(1) indicates a mismatch between the LPOST image on disk and the LPOST
image flashed in a System Board. (2) indicates that not all boards
within the domain are flashed with the same LPOST version. (2) implies
(1).
This issue occurs due to the interchangeability of System Boards between
Sun Fire 12K/15K systems and Sun Fire 3800-6800 systems. Another
factor is the need to periodically update firmware to provide product
enhancements.
This issue is addressed by permitting LPOST flashupdates to occur with
domains running, which significantly simplifies the update process.
Downtime is no longer incurred, and mismatched versions and/or upgrades
are addressed in a more timely fashion.
See details below for flashupdating Sun Fire 12K/15K System Boards.
IMPLEMENTATION:
---
| | MANDATORY (Fully Proactive)
---
---
| | CONTROLLED PROACTIVE (per Sun Geo Plan)
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| X | REACTIVE (As Required)
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CORRECTIVE ACTION:
The following recommendation is provided as a guideline for authorized
Sun Services Field Representatives who may encounter the above
mentioned problem.
In general, when a new CPU/MCPU board is introduced into the
platform, it should be flashupdated to the LPOST version installed
on the SC. Regardless of an upgrade or downgrade, consistency of
LPOST images is the goal. For example, if SB17 is installed into the
system, check the LPOST image flashed on the board:
% flashupdate -f /opt/SUNWSMS/hostobjs/sgcpu.flash SB17
Current System Board FPROM Information
======================================
CPU at SB17, FPROM 0:
POST 09/04/02 02:57:00 PM Release 5.13.3 Build 4.0 I/F 12
OBP 09/04/02 02:57:00 PM Release 5.13.3 Build 4.0
Ver 09/04/02 02:57:00 PM Release 5.13.3 Build 4.0
CPU at SB17, FPROM 1:
POST 09/04/02 02:57:00 PM Release 5.13.3 Build 4.0 I/F 12
OBP 09/04/02 02:57:00 PM Release 5.13.3 Build 4.0
Ver 09/04/02 02:57:00 PM Release 5.13.3 Build 4.0
Flash Image Information
========================
POST 09/04/02 02:57:00 PM Release 5.13.3 Build 4.0 I/F 12
OBP 09/04/02 02:57:00 PM Release 5.13.3 Build 4.0
Ver 09/04/02 02:57:00 PM Release 5.13.3 Build 4.0
Do you wish to update the FPROM (yes/no)?
If the on-board image differs (uprev or downrev) from the Flash Image,
answer 'Y' and update the board.
Conversely, if an updated flash image is installed on the System
Controller via an SMS patch, CPU/MCPU boards should be flashupdated
with the updated LPOST image. It is generally desired to flash CPU/MCPU
boards to the latest LPOST image available. A listing of current images
is at http://pts-americas.west/esg/hsg/starcat/xctt/sms_firmware.html.
The flashupdate can be done with domains up and running. This has been
tested and proven to work. However, there are some situations to be
aware of. An LPOST image contains some routines that in a few cases are
required by a running domain. These routines are needed in the following
situations:
o POST runs on the board/domain
This occurs when a CPU/MCPU board is DR attached to a domain, or as
part of an ASR recovery (reboot, panic, Dstop).
If such an act occurs while a CPU/MCPU board is being flashupdated,
POST will fail some/all of the processors on that board. In the case
of DR, this may result in the failure of the DR operation. In the
case of an ASR recovery, other boards with intact LPOST images are
not effected, so provided multiple CPU boards exist within the domain,
the domain will survive minus 1 or more processors.
o Processors are issued XIR
dsmd will issue XIRs to processors as part of some ASR recoveries
(heartbeat failures, for example). Also, the 'reset' CLI issues
XIR.
If an XIR occurs while a CPU/MCPU board is being flashupdated, XIR
information for processors on that board is incomplete/invalid.
If any of the situations above occurs during flashupdate, the
flashupdate process will report an error. For example:
Update CPU at SB1, FPROM 0:
Erasing...
Done.
Writing and verifying ...
Error on write and verify.
Update CPU at SB1, FPROM 1:
Erasing...
Error on erasing FPROM 1.
Any interrupted flashupdates must be corrected. Thus, when flashupdating
boards in running domains:
. Avoid usage of DR during the flashupdate
. Avoid usage of 'reset' during the flashupdate
. Watch for any domain recoveries that may occur during the
flashupdate and take corrective action immediately
For planning purposes, a typical flashupdate of a single CPU board
takes on average 7.5 minutes to complete.
NOTE: An alternative to flashupdating boards in a running domain is to
individually DR detach each board, flash its FPROMs, then DR
attach the board again.
COMMENTS:
None.
============================================================================
Implementation Footnote:
i) In case of MANDATORY FINs, Sun Services will attempt to contact
all affected customers to recommend implementation of the FIN.
ii) For CONTROLLED PROACTIVE FINs, Sun Services mission critical
support teams will recommend implementation of the FIN (to their
respective accounts), at the convenience of the customer.
iii) For REACTIVE FINs, Sun Services will implement the FIN as the
need arises.
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