C H A P T E R

C H A P T E R 36

Cache Consistency Test (mpconstest)

mpconstest verifies that cache coherency is maintained in a multi-processor environment by creating contention for one or more cache lines.

Only the following cpus are supported:

SuperSPARC [TI] (SS10/SS20/SS1000/SC2000)
SuperSPARC II
MicroSPARC II [TI] (50 MHz)
MicroSPARC II (SS5)
UltraSPARC I [TI] (143/167/200MHz)
UltraSPARC II (250/333/336/360MHz)
UltraSPARC III (500-600/750/900MHz)
UltraSPARC III Cu

This test has several subtests, each designed to create a different kind of contention for cache lines. Each subtest uses different methods to test the shared memory buffer, the stride size, and any intermediate stores or loads.

When mpconstest starts, it creates a shared memory buffer. It then determines the number of CPUs on the system. For each CPU, the test takes the following steps:

Forks a thread and binds it to the CPU.
Runs the selected subtest in the thread.
Assigns each CPU an ID number from 1 to n . The CPU assigned ID 1 is considered the master.

The above steps are repeated for each subtest. Only one subtest can be selected at a time.

This test is not scalable.

mpconstest Test Requirements

This test requires that the tested system has at least two CPUs. Otherwise, the test will not appear as an option.

mpconstest only runs on machines that support the v8plus standard of SPARC CPU hardware architecture. If the v8plus instructions are not supported, mpconstest will not appear on the Test Selection GUI. To determine whether a machine supports the v8plus standard, go to a command prompt on that machine and type:

% isalist

sparcv9+vis sparcv9 sparcv8plus+vis sparcv8plus sparcv8

Note Note - This set of tests is very sensitive to activity on the machine and must be run exclusive of all other tests.

mpconstest Subtests

TABLE 36-1 `mpconstest` subtests
Tests	Description
cons1	Each CPU writes to successive locations with a stride size of byte, half word, or full word. This subtest creates contention for a single cache line. No other loads or stores are performed between successive writes to shared memory.
cons2	Each CPU reads from a location that is cachesize bytes away from the last written location. Every read causes the previously written line to be written back. The test runs until the CPU has accessed all lines in the cache.
cons3	Similar to cons1 except that only one double word of each line is accessed. This creates simultaneous contention for multiple cache lines rather than a single line.
cons4	Similar to cons2, except that each CPU performs one store byte ( `storeb` ) and one load byte ( `loadb` ) operation between the detection of ID and the write of the next CPU ID. The target of the `storeb` and `loadb` is a unique byte in the line the CPU just read. This target is recognized as a different double word in the shared line cachesize bytes.
cons5	Similar to cons3 except that each CPU performs one `storeb` and one `loadb` operation between the detection of ID and the write of the next CPU ID. The target of the `storeb` is one unique byte of the next double word in the line that the CPU just read from the CPU ID. The `storeb` data is unique to each CPU and changes each time the address of the target line changes.
cons6	Similar to cons1 except that only one double word of each line is accessed. This creates simultaneous contention for multiple cache lines rather than a single line.
cons7	Similar to cons3 except that each CPU performs two `storeb` and one `loadh` operations between the detection of the CPU ID and the write of the next CPU ID. The targets of the `storebs` and `loadh` are two consecutive bytes of a double word in a shared line which is not a part of the shared memory buffer containing the IDs. The address of the target `storeb` and `loadh` instructions is held constant. The first `storeb` instruction gains ownership of the cache line, and the second `stroreb` is performed as a write hit. This occurs at the same time other CPUs are reading and writing the shared line containing the IDs.
cons8	Similar to cons3 except that each CPU performs one `storeb` and one `loadb` operation between the detection of the CPU ID and the write of the next CPU ID. The target of the `storeb` and `loadb` is one unique byte of a double word of a private (unshared) line whose line number is identical to the line number containing the IDs. The `storeb` data is unique to each CPU and changes each time the address of the line containing the IDs changes.
cons9	Similar to cons8 except that the target of the `storeb` and `loadb` is one unique byte of a double word of a private line whose address does not change through the entire test.
cons10	Similar to cons9 except that two `storeb` and two `loadb` operations are performed to private (unshared) lines.The target of the second `storeb` is cachesize bytes away from the target of the first `storeb` . In a direct map cache, this results in a writeback of the unshared data written with the first `storeb` . The `loadb` operations are performed after the `storeb` in order to ensure that the writeback occurs correctly.
cons11	Similar to cons10 except that the target of the `storeb` and `loadb` operations is to a shared line rather than a private line.
cons12	Similar to cons7 except that two store double ( `stored` ) and load double ( `loadd` ) operations are used in place of the `storeb` and `loadb` operations. The target of the `stored` and `loadd` operations are two consecutive double words of a shared line. This test is designed to verify that the double word operations are performed correctly while the shared and owned state of the line containing the ID is changing.
cons13 through cons17	These tests are similar variations of intermediate operations, stride size etc, and do not involve any new interfaces.

mpconstest Options

To reach the dialog box below, right-click on the test name in the System Map and select Test Parameter Options. If you do not see this test in the System Map, you might need to expand the collapsed groups, or your system may not include the device appropriate to this test. Refer to the SunVTS User's Guide for more details.

FIGURE 36-1 mpconstest Test Parameter Options Dialog Box

TABLE 36-2 `mpconstest` Options
Option	Description
Test Name	Selects the subtest to be run.
Number of Timeout Iterations	Sets the number of times the test is allowed to time out. Default is 1. Note that each timeout occurs after a greater amount of elapsed time than the previous one. That is, if the first timeout occurs after `T` units of time, the second occurs `2T` after `T` , and the third occurs `3T` after `2T` .
Lock Buffer	Locks Buffer in Memory. Default is not locked. Locking the buffer in memory will disable COMA (Cache Only Memory Architecture).
Atomic Mode	Uses the atomic instruction swap. Default is disabled.
Byte Mode	Uses byte instructions to load and store. Default is disabled.
Immediate Mode	Supports all subtests except cons1, cons2, cons3, cons15, cons16, and cons17.
Random Mode	Enables Random Mode.
Reverse Mode	Traverses the shared memory buffer in reverse. Default is disabled.
Prefetch Mode	Sets prefetch for read and write. Default is disabled.
CoreFile	Generates a core file. Exits in case of unexpected signals. Default is disabled.
Ecache Disable	Disables the external cache. Default is enabled.
Trigger	Sends an interrupt signal to all processors when one processor detects a failure. Default is disabled.
Offset	Specifies an offset of line size between successive writes. Default is disabled.
CPU Wait Count	Forces CPU 1 to write first if the number of CPUs is less than cpucount . Default is disabled. This option is not supported with subtests cons15, cons16, and cons17.
Number of Loops	Selects the number of test loops. Default is 5.
Number of Passes	Selects the number of passes. Increasing the number of passes increases system stress. Setting the number of passes to 0 will cause the test to run in an endless loop. Passes can only be set to 0 in command line mode, not from the GUI. Default is 1.
Memory Size	Selects the memory size, in Megabytes, for the shared buffer. Default is 128.
Random Mode Seed	Sets random number seed to a user specified value. Selects a random number seed by default.

mpconstest Test Modes

TABLE 36-3 `mpconstest` Test Modes
Test Mode	Supported?	Description
Connection	No	Not supported.
Functional (Offline)	Yes	Runs the full test.

mpconstest Command-Line Syntax

/opt/SUNWvts/bin/mpconstest standard_arguments -o tst= Cons1|Cons2 ,itm= number ,lck,a,b,c,e,h,loops= number ,memsize= memsize , wait= cpucount ,passes= passes ,r, t,x,y,i,q,seed =number

TABLE 36-4 `mpconstest` Command-Line Syntax
Argument	Description
`tst=` Cons1\|Cons2\|Cons3\|Cons4\| Cons5\|Cons6\| Cons7\|Cons8\| Cons9\|Cons10\| Cons11\|Cons12\| Cons12\|Cons13\| Cons14\|Cons15\| Cons16\|Cons17	Range of choices available between cons1 through cons17 subtests.
`itm=` number	Sets the number of times the test is allowed to time out. Default is 1. Note that each timeout occurs after a greater amount of elapsed time than the previous one. That is, if the first timeout occurs after `T` units of time, the second occurs `2T` after `T` , and the third occurs `3T` after `2T` .
`lck`	Locks Buffer in Memory. Default is not locked. Locking the buffer in memory will disable COMA (Cache Only Memory Architecture).
`a`	Enables atomic mode. Uses the atomic instruction swap
`b`	Enables byte mode. Uses byte instructions to load and store.
`c`	Generates a core file. Exits in case of unexpected signals.
`e`	Disables the external cache.
`h`	Prints usage message.
`loops=` number	Sets the number of loops for the iterations. Default is 5.
`memsize=` memsize	Selects the memory size, in Megabytes, for the shared buffer. Default is 128.
`wait=` cpucount	Forces CPU 1 to write first if the number of CPUs is less than cpucount .
`passes=` passes	Selects the number of passes. Increasing the number of passes increases system stress. Setting the number of passes to 0 will cause the test to run in an endless loop. Passes can only be set to 0 in command line mode, not from the GUI. Default is 1.
`r`	Enables Reverse mode. Traverses the shared memory buffer in reverse.
`t`	Enables Trigger. Sends an interrupt signal to all processors when one processor detects a failure.
`x`	Enables Prefetch. Sets prefetch for read and write.
`y`	Enables Offset. Specifies an offset of line size between successive writes.
`i`	Enables Immidiate Mode. Not suppored for subtests cons1, cons2, cons3, cons15, and cons 17.
`q`	Enables Random Mode.
`seed`	Sets a random number seed to the user specified value.