- Problem Statement: 

L2 Check error (prerequest not equal predicted value)

- Symptoms:

AR IO12  L2_Check_Err[28:0] = 00009818
        L2CErr[    3]:   1E  Port 8 prerequest not equal predicted value
        L2CErr[    4]:   1E  Port 9 prerequest not equal predicted value
        L2CErr[   11]:   1E  Port 8 command valid not equal predicted value
        L2CErr[   12]:   1E  Port 9 command valid not equal predicted value
FAIL Slot IO12:  Dstop detected by AR.
Primary service FRU is Slot IO12.
SDI EX13/S0: All SDI is DStopped and RStopped, requested by DARB.            

- Troubleshooting:

The parts involved for a normal AR (Address Repeater)
L1-L2 (Level 1 to Level 2) transaction are:
slot0 SB, slot1 O/B bd OR Maxcat, & EXB

Recall that the EXB is the L2 Address Repeater, and the slot0, slot1, and exb make up
the complete board set, sometimes called a snoopy coherence domain.

The L2 check is actually performed at the L1 board, and so the L1 board is the board
that is called out.

The problem is either caused by the L1 board or the EXB.

Basically the L1 board predicts when the L2 will be sending a transaction. When the
prediction is wrong, the L2 check error occurs.

- Resolution:

First replace the L1 board shown in the dstop wfail output.
If this does not solve the problem, replace the exb.


- Summary of part number and patch ID's 

p/n 501-6376 System Expander Board Assembly
p/n 501-5397 hsPCI Board without PCI Cassettes
NOTE: There are several SB p/n's depending on how much RAM, etc.
      Only one is listed here.
p/n 540-5052 Sun Fire CPU/Memory Board with 4 UltraSPARC III 
             900MHZ 0MB   
p/n 501-6138  MaxCPU Board 900MHz
        
- References and bug IDs
 Ar (Address Repeater spec.)

- Additional background information:

When the L2 AR wants to issue a transaction packet to an L1 AR, it does so without
having to go through any arbitration. It is assumed that the L1 AR will accurately
predict that the L2 AR will drive and will therefore not be driving itself.

The L2 does assert AR_PREREQ_L on the L2 interface in the same
cycle in which it drives the transaction. This signal allows the L1 to perform a
consistency check to verify that it is accurately predicting the behavior of the L2 AR.

In order for any given L1 to know how the L2 will behave, it must be made aware of
every transaction sent to the L2. It must also know from which L1 AR each transaction
is sent out. To facilitate this, each L1 AR asserts AR_L1_CMD_OUT_L at the same time
it drives a transaction to the L2 AR.

On the receiving end, the other AR in the snoopy coherence domain, will see the first
AR's cmd out on its AR_L1_CMD_IN_L line.

With this scheme, every L1 knows exactly how many entries are in each of the L2 AR's
incoming request queues (IRQ). Each L1 then implements the exact same arbitration scheme
as the L2. By doing this, each L1 can predict, for every cycle, which L1-L2 interfaces
will be driven by the L2 AR.

- Meta-Data/Problem categorization:

Product/Platform: SF15K
Category:

- Keywords

L2_Check_Err L2 Check error prerequest predicted