The 8051 is definitive not a good choice to calculate with a large amount
of data.
But some applications need only collect data over a long time (logging data).
In most cases such data must also be hold during power off. An easy solution
be using serial EEPROM e.g. 24C256. If you need more size, faster write or
many write cycle you can use battery powered SRAM e.g. HM628512 to store
512kByte.
But there are some disadvantages on using SRAM. You need a high count of
connections to the MCU and special circuits to prevent data altering during
power off and power on.
I use an own MCU (AT90S1200) to access the SRAM. So only 4 connections
needed (clock, data, ground, vcc).
Why the AT90S1200 ? There are 2 advantages to the AT89C2051: The higher execution
speed and the return from power down by the external interrupt. But the interrupt
can only activated by low level. Since the external circuit goes low on power
off, T1 was needed to invert the level. Another disadvantage of the AT90S1200
is the wrong internal power on reset. It works only on very fast rising supply
voltage but the big capacitor allow only slow rising. So J1 was needed to
manually reset on the first power on.
If external power was removed, the AT90S1200 goes in power down and consume
down to 100nA. So a capacitor of 1Farad (Goldcap) can hold data up to 2 months
or 2200µF over 8 hours.
The data lines are direct driven by the AT90S1200 and the address signals
simple generated by shift registers. Only by adding a 3. 74HCT164 you can
access up to 128MByte SRAM.
The clock speed is not important. The given values generate about 8MHz. On
a lower external data speed you can also use the internal clock (1MHz).
The circuit must be driven by open drain outputs since the clock drive the
transistor (high = 0.7V) and the data line was used bidirectional.
The timing was optimized to generate it by software. Both changing of clock
was used to transfer data.
"DO" and "DI" are the same line. They explain only the data direction (DO:
send data to the SRAM module).
A data transfer must be started by 2 changes of the DIO line (1-0-1) during
CLK high. After start you must finished the transfer within 30ms. Otherwise
the AT90S1200 goes in power down (if CLK = 0) or waiting for the next start
condition. This seems enough time to serve also interrupts during
transfers.
The next 2 bits define the sort of data transfer:
| 00 | read command byte |
| 10 | write command byte |
| 01 | read address / data byte |
| 11 | write address / data byte |
Command byte:
| Bit 0 |
0 = read / write address, 3 Bytes, LSB first, read / write command reset to LSB |
1 = read / write data |
| Bit 1 | 1 = increment address after read | |
| Bit 2 | 0 = read only | 1 = write enabled |
| Bit 3 | 1 = increment address after write | |
| Bit 4 | 1 = increment address | |
| Bit 5 | reserved | |
| Bit 6 | reserved | |
| Bit 7 | reserved |
Automatic increment the address after read or write make it easy to transfer
more bytes.
All transfers are receipt by low level (acknowledge). After the last 0-1
transition of CLK the low level was removed if the SRAM module ready to next
transfer.
With an AT89C51 at 14.7456MHz you can generate the timing fast as
possible.
After CLK = 0 for more the 30ms the module goes in power down. This was marked
by pulling DIO low. 16ms after setting CLK = 1 the module wake up and pull
down of DIO was released.
For more details contact me: Peter Dannegger