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E.  SPARC-V9 Instruction Set E.2 SPARC-V9 Instruction Set Changes E.2.3 Added Instructions to Support High-Performance System Implementation  Previous   Contents   Next 
   
 

E.2.4 Deleted Instructions

Table E-8

Coprocessor loads and stores

 

RDTBR and WRTBR

TBR no longer exists. It is replaced by TBA, which can be read/written with RDPR/WRPR instructions

RDWIM and WRWIM

WIM no longer exists. WIM has been replaced by several register-window registers

REPSR and WRPSR

PSR no longer exists. It has been replaced by several separate registers that are read/written with other instructions

RETT

Return from trap (replace by DONE/RETRY)

STDFQ

Store Double from Floating-point Queue (replaced by the RDPR FQ instruction

E.2.5 Miscellaneous Instruction Changes

Table E-9

IMPDEPn

(Changed) Implementation-dependent instructions (replace SPARC-V8 CPop instructions)

MEMBAR

(Added) Memory barrier (memory synchronization support)

E.3 SPARC-V9 Instruction Set Mapping

Table E-10

Opcode

Mnemonic

Argument List

Operation

Comments

 

BPA

 

ba{,a}

{,pt|,pn}

 

%icc or %xcc, label

(Branch on cc with prediction)

Branch always

 

1

BPN

bn{,a}

{,pt|,pn}

%icc or %xcc, label

Branch never

0

BPNE

bne{,a}

{,pt|,pn}

%icc or %xcc, label

Branch on not equal

not Z

BPE

be{,a}

{,pt|,pn}

%icc or %xcc, label

Branch on equal

Z

BPG

bg{,a}

{,pt|,pn}

%icc or %xcc, label

Branch on greater

not (Z or (N xor V))

BPLE

ble{,a}

{,pt|,pn}

%icc or %xcc, label

Branch on less or equal

Z or (N xor V)

BPGE

bge{,a}

{,pt|,pn}

%icc or %xcc, label

Branch on greater or equal

not (N xor V)

BPL

bl{,a}

{,pt|,pn}

%icc or %xcc, label

Branch on less

N xor V

BPGU

bgu{,a}

{,pt|,pn}

%icc or %xcc, label

Branch on greater unsigned

not (C or Z)

BPLEU

bleu{,a}

{,pt|,pn}

%icc or %xcc, label

Branch on less or equal unsigned

C or Z

BPCC

bcc{,a}

{,pt|,pn}

%icc or %xcc, label

Branch on carry clear (greater than or equal, unsigned)

not C

BPCS

bcs{,a}

{,pt|,pn}

%icc or %xcc, label

Branch on carry set (less than, unsigned)

C

BPPOS

bpos{,a}

{,pt|,pn}

%icc or %xcc, label

Branch on positive

not N

BPNEG

bneg{,a}

{,pt|,pn}

%icc or %xcc, label

Branch on negative

N

BPVC

bvc{,a}

{,pt|,pn}

%icc or %xcc, label

Branch on overflow clear

not V

BPVS

bvs{,a}

{,pt|,pn}

%icc or %xcc, label

Branch on overflow set

V

BRZ

brz{,a}

{,pt|,pn}

regrs1, label

Branch on register zero

Z

BRLEZ

brlez{,a}

{,pt|,pn}

regrs1, label

Branch on register less than or equal to zero

N or Z

BRLZ

brlz{,a}

{,pt|,pn}

regrs1, label

Branch on register less than zero

N

BRNZ

brnz{,a}

{,pt|,pn}

regrs1, label

Branch on register not zero

not Z

BRGZ

brgz{,a}

{,pt|,pn}

regrs1, label

Branch on register greater than zero

not (N or Z)

BRGEZ

brgez{,a}

{,pt|,pn}

regrs1, label

Branch on register greater than or equal to zero

not N

CASA

casa

casa

[regrs1]imm_asi,regrs2,regrd

[regrs1]%asi,regrs2,regrd

Compare and swap word from alternate space

 

CASXA

casxa

casxa

[regrs1]imm_asi,regrs2,regrd

[regrs1]%asi,regrs2,regrd

Compare and swap extended from alternate space

 

 

FBPA

 

fba{,a}

{,pt|,pn}

 

%fccn, label

(Branch on cc with prediction)

Branch never

 

1

FBPN

fbn{,a}

{,pt|,pn}

%fccn, label

Branch always

0

FBPU

fbu{,a}

{,pt|,pn}

%fccn, label

Branch on unordered

U

FBPG

fbg{,a}

{,pt|,pn}

%fccn, label

Branch on greater

G

FBPUG

fbug{,a}

{,pt|,pn}

%fccn, label

Branch on unordered or greater

G or U

FBPL

fbl{,a}

{,pt|,pn}

%fccn, label

Branch on less

L

FBPUL

fbul{,a}

{,pt|,pn}

%fccn, label

Branch on unordered or less

L or U

FBPLG

fblg{,a}

{,pt|,pn}

%fccn, label

Branch on less or greater

L or G

FBPNE

fbne{,a}

{,pt|,pn}

%fccn, label

Branch on not equal

L or G or U

FBPE

fbe{,a}

{,pt|,pn}

%fccn, label

Branch on equal

E

FBPUE

fbue{,a}

{,pt|,pn}

%fccn, label

Branch on unordered or equal

E or U

FBPGE

fbge{,a}

{,pt|,pn}

%fccn, label

Branch on greater or equal

E or G

FBPUGE

fbuge{,a}

{,pt|,pn}

%fccn, label

Branch on unordered or greater or equal

E or G or U

FBPLE

fble{,a}

{,pt|,pn}

%fccn, label

Branch on less or equal

E or L

FBPULE

fbule{,a}

{,pt|,pn}

%fccn, label

Branch on unordered or less or equal

E or L or u

FBPO

fbo{,a}

{,pt|,pn}

%fccn, label

 

Branch on ordered

E or L or G

FLUSHW

flushw

 

Flush register windows

 

 

FMOVA

 

fmov

{s,d,q}a

 

%icc or %xcc, fregrs2, fregrd

(Move on integer cc)

Move always

 

1

FMOVN

fmov

{s,d,q}n

%icc or %xcc, fregrs2, fregrd

Move never

0

FMOVNE

fmov

{s,d,q}ne

%icc or %xcc, fregrs2, fregrd

Move if not equal

not Z

FMOVE

fmov

{s,d,q}e

%icc or %xcc, fregrs2, fregrd

Move if equal

Z

FMOVG

fmov

{s,d,q}g

%icc or %xcc, fregrs2, fregrd

Move if greater

not (Z or (N xor V))

FMOVLE

fmov

{s,d,q}le

%icc or %xcc, fregrs2, fregrd

Move if less or equal

Z or (N xor V)

FMOVGE

fmov

{s,d,q}ge

%icc or %xcc, fregrs2, fregrd

Move if greater or equal

not (N xor V)

FMOVL

fmov

{s,d,q}l

%icc or %xcc, fregrs2, fregrd

Move if less

N xor V

FMOVGU

fmov

{s,d,q}gu

%icc or %xcc, fregrs2, fregrd

Move if greater unsigned

not (C or Z)

FMOVLEU

fmov

{s,d,q}leu

%icc or %xcc, fregrs2, fregrd

Move if less or equal unsigned

C or Z

FMOVCC

fmov

{s,d,q}cc

%icc or %xcc, fregrs2, fregrd

Move if carry clear (greater or equal, unsigned)

not C

FMOVCS

fmov

{s,d,q}cs

%icc or %xcc, fregrs2, fregrd

Move if carry set (less than, unsigned)

C

FMOVPOS

fmov

{s,d,q}pos

%icc or %xcc, fregrs2, fregrd

Move if positive

not N

FMOVNEG

fmov

{s,d,q}neg

%icc or %xcc, fregrs2, fregrd

Move if negative

N

FMOVVC

fmov

{s,d,q}vc

%icc or %xcc, fregrs2, fregrd

Move if overflow clear

not V

FMOVVS

fmov

{s,d,q}vs

%icc or %xcc, fregrs2, fregrd

Move if overflow set

V

 

FMOVRZ

 

fmovr

{s,d,q}e

 

regrs1, fregrs2, fregrd

(Move f-p register on cc)

Move if register zero

 

FMOVRLEZ

fmovr

{s,d,q}lz

regrs1, fregrs2, fregrd

Move if register less than or equal zero

 

FMOVRLZ

fmovr

{s,d,q}lz

regrs1, fregrs2, fregrd

Move if register less than zero

 

FMOVRNZ

FMOVRGZ

FMOVRGEZ

fmovr

{s,d,q}ne

fmovr

{s,d,q}gz

fmovr

{s,d,q}gez

regrs1, fregrs2, fregrd

regrs1, fregrs2, fregrd

regrs1, fregrs2, fregrd

Move if register not zero

Move if register greater than zero

Move if register greater than or equal to zero

 

FMOVFA

FMOVFN

FMOVFU

FMOVFG

FMOVFUG

FMOVFL

FMOVFUL

FMOVFLG

FMOVFNE

FMOVFE

FMOVFUE

FMOVFGE

FMOVFUGE

FMOVFLE

FMOVFULE

FMOVFO

 

fmov{s,d,q}a

fmov{s,d,q}n

fmov{s,d,q}u

fmov{s,d,q}g

fmov{s,d,q}ug

fmov{s,d,q}l

fmov{s,d,q}ul

fmov{s,d,q}lg

fmov{s,d,q}ne

fmov{s,d,q}e

fmov{s,d,q}ue

fmov{s,d,q}ge

fmov{s,d,q}uge

fmov{s,d,q}le

fmov{s,d,q}ule

fmov{s,d,q}o

%fccn,fregrs2,fregrd

%fccn,fregrs2,fregrd

%fccn,fregrs2,fregrd

%fccn,fregrs2,fregrd

%fccn,fregrs2,fregrd

%fccn,fregrs2,fregrd

%fccn,fregrs2,fregrd

%fccn,fregrs2,fregrd

%fccn,fregrs2,fregrd

%fccn,fregrs2,fregrd

%fccn,fregrs2,fregrd

%fccn,fregrs2,fregrd

%fccn,fregrs2,fregrd

%fccn,fregrs2,fregrd

%fccn,fregrs2,fregrd

%fccn,fregrs2,fregrd

 

(Move on floating-point cc)

Move always

Move never

Move if unordered

Move if greater

Move if unordered or greater

Move if less

Move if unordered or less

Move if less or greater

Move if not equal

Move if equal

Move if unordered or equal

Move if greater or equal

Move if unordered or greater or equal

Move if less or equal

Move if unordered or less or equal

Move if ordered

1

0

U

G

G or U

L

L or U

L or G

L or G or U

E

E or U

E or G

E or G or U

E or L

E or L or u

E or L or G

LDSW

LDSWA

ldsw

ldsw

[address], regrd

[regaddr] imm_asi, regrd

Load a signed word

Load signed word from alternate space

 

LDX

LDXA

 

LDXFSR

ldx

ldxa

ldxa

ldx

[address], regrd

[regaddr] imm_asi, regrd

[reg_plus_imm] %asi, regrd

[address], %fsr

Load extended word

Load extended word from alternate space

Load floating-point state register

 

MEMBAR

membar

membar_mask

Memory barrier

 

MOVA

MOVN

MOVNE

MOVE

MOVG

MOVLE

MOVGE

MOVL

MOVGU

MOVLEU

MOVCC

MOVCS

MOVPOS

MOVNEG

MOVVC

MOVVS

mova

movn

movne

move

movg

movle

movge

movl

movgu

movleu

movcc

movcs

movpos

movneg

movvc

movvs

%icc or %xcc, reg_or_imm11, regrd

%icc or %xcc, reg_or_imm11, regrd

%icc or %xcc, reg_or_imm11, regrd

%icc or %xcc, reg_or_imm11, regrd

%icc or %xcc, reg_or_imm11, regrd

%icc or %xcc, reg_or_imm11, regrd

%icc or %xcc, reg_or_imm11, regrd

%icc or %xcc, reg_or_imm11, regrd

%icc or %xcc, reg_or_imm11, regrd

%icc or %xcc, reg_or_imm11, regrd

%icc or %xcc, reg_or_imm11, regrd

%icc or %xcc, reg_or_imm11, regrd

%icc or %xcc, reg_or_imm11, regrd

%icc or %xcc, reg_or_imm11, regrd

%icc or %xcc, reg_or_imm11, regrd

%icc or %xcc, reg_or_imm11, regrd

(Move integer register on cc)

Move always

Move never

Move if not equal

Move if equal

Move if greater

Move if less or equal

Move if greater or equal

Move if less

Move if greater unsigned

Move if less or equal unsigned

Move if carry clear (greater or equal, unsigned)

Move if carry set (less than, unsigned)

Move if positive

Move if negative

Move if overflow clear

Move if overflow set

1

0

not Z

Z

not (Z or (N xor V))

Z or (N xor V)

not (N xor V)

N xor V

not (C or Z)

C or Z

not C

C

not N

N

not V

V

MOVFA

MOVFN

MOVFU

MOVFG

MOVFUG

MOVFL

MOVFUL

MOVFLG

MOVFNE

MOVFE

MOVFUE

MOVFGE

MOVFUGE

MOVFLE

MOVFULE

MOVFO

mova

movn

movu

movg

movug

movl

movul

movlg

movne

move

movue

movge

movuge

movle

movule

movo

%fccn,reg_or_imm11,regrd

%fccn,reg_or_imm11,regrd

%fccn,reg_or_imm11,regrd

%fccn,reg_or_imm11,regrd

%fccn,reg_or_imm11,regrd

%fccn,reg_or_imm11,regrd

%fccn,reg_or_imm11,regrd

%fccn,reg_or_imm11,regrd

%fccn,reg_or_imm11,regrd

%fccn,reg_or_imm11,regrd

%fccn,reg_or_imm11,regrd

%fccn,reg_or_imm11,regrd

%fccn,reg_or_imm11,regrd

%fccn,reg_or_imm11,regrd

%fccn,reg_or_imm11,regrd

%fccn,reg_or_imm11,regrd

(Move on floating-point cc)

Move always

Move never

Move if unordered

Move if greater

Move if unordered or greater

Move if less

Move if unordered or less

Move if less or greater

Move if not equal

Move if equal

Move if unordered or equal

Move if greater or equal

Move if unordered or greater or equal

Move if less or equal

Move if unordered or less or equal

Move if ordered

1

0

U

G

G or U

L

L or U

L or G

L or G or U

E E or U

E or G

E or G or U

E or L

E or L or u

E or L or G

MOVRZ

MOVRLEZ

MOVRLZ

MOVRNZ

MOVRGZ

MOVRGEZ

movre

movrlez

movrlz

movrnz

movrgz

movrgez

regrs1, reg_or_imm10,regrd

regrs1, reg_or_imm10,regrd

regrs1, reg_or_imm10,regrd

regrs1, reg_or_imm10,regrd

regrs1, reg_or_imm10,regrd

regrs1, reg_or_imm10,regrd

(Move register on register cc)

Move if register zero

Move if register less than or equal to zero

Move if register less than zero

Move if register not zero

Move if register greater than zero

Move if register greater than or equal to zero

Z

N or Z

N

not Z

N nor Z

not N

MULX

mulx

regrs1, reg_or_imm,regrd

(Generic 64-bit Multiply) Multiply (signed or unsigned)

See SDIVX and UDIVX

POPC

popc

reg_or_imm, regrd

Population count

 

PREFETCH

PREFETCHA

prefetch

prefetcha

prefetcha

[address], prefetch_dcn [regaddr] imm_asi, prefetch_fcn [reg_plus_imm] %asi, prefetch_fcn

Prefetch data

Prefetch data from alternate space

See The SPARC architecture manual, version 9

 

SDIVX

sdivx

regrs1, reg_or_imm,regrd

(64-bit signed divide) Signed Divide

See MULX and UDIVX

STX

STXA

 

STXFSR

stx

stxa

stxa

stx

regrd, [address]

regrd, [address] imm_asi

regrd, [reg_plus_imm] %asi %fsr, [address]

Store extended word

Store extended word into alternate space

 

Store floating-point register (all 64-bits)

 

UDIVX

udivx

regrs1, reg_or_imm, regrd

(64-bit unsigned divide) Unsigned divide

See MULX and SDIVX

E.4 SPARC-V9 Floating-Point Instruction Set Mapping

SPARC-V9 floating-point instructions are shown in the following table.

Table E-11

SPARC

Mnemonic1

Argument List

Description

F[sdq]TOx

fstox

fdtox

fqtox

fregrs2, fregrd

fregrs2, fregrd

fregrs2, fregrd

Convert floating point to 64-bit integer

fstoi

fdtoi

fqtoi

fregrs2, fregrd

fregrs2, fregrd

fregrs2, fregrd

Convert floating-point to 32-bit integer

FxTO[sdq]

fxtos

fxtod

fxtoq

fregrs2, fregrd

fregrs2, fregrd

fregrs2, fregrd

Convert 64-bit integer to floating point

fitos

fitod

fitoq

fregrs2, fregrd

fregrs2, fregrd

fregrs2, fregrd

Convert 32-bit integer to floating point

FMOV[dq]

fmovd

fmovq

fregrs2, fregrd

fregrs2, fregrd

Move double

Move quad

FNEG[dq]

fnegd

fnegq

fregrs2, fregrd

fregrs2, fregrd

Negate double

Negate quad

FABS[dq]

fabsd

fabsq

fregrs2, fregrd

fregrs2, fregrd

Absolute value double

Absolute value quad

LDFA

 

LDDFA

 

LDQFA

lda

lda

ldda

ldda

ldqa

ldqa

[regaddr] imm_asi, fregrd

[reg_plus_imm] %asi, fregrd

[regaddr] imm_asi, fregrd

[reg_plus_imm] %asi, fregrd

[regaddr] imm_asi, fregrd

[reg_plus_imm] %asi, fregrd

Load floating-point register from alternate space

Load double floating-point register from alternate space.

Load quad floating-point register from alternate space

STFA

 

STDFA

 

STQFA

sta

sta

stda

stda

stqa

stqa

fregrd, [regaddr] imm_asi

fregrd, [reg_plus_imm] %asi

fregrd, [regaddr] imm_asi

fregrd, [reg_plus_imm] %asi

fregrd, [regaddr] imm_asi

fregrd, [reg_plus_imm] %asi

Store floating-point register to alternate space

Store double floating-point register to alternate space

Store quad floating-point register to alternate space

1 Types of Operands are denoted by the following lower-case letters:i 32-bit integerx 64-bit integers singled doubleq quad

E.5 SPARC-V9 Synthetic Instruction-Set Mapping

Here is a mapping of synthetic instructions to hardware equivalent instructions.

Table E-12

Synthetic Instruction

Hardware Equivalent(s)

Comment

cas

casl

casx

casxl

[regrsl], regrs2, regrd

[regrsl], regrs2, regrd

[regrsl], regrs2, regrd

[regrsl], regrs2, regrd

casa

casa

casxa

casxa

[regrsl]ASI_P, regrs2, regrd

[regrsl]ASI_P_L, regrs2, regrd

[regrsl]ASI_P, regrs2, regrd

[regrsl]ASI_P_L, regrs2, regrd

Compare & swap (cas)

cas little-endian

cas extended

cas little-endian, extended

clrx

[address]

stx

%g0, [address]

Clear extended word

clruw

clruw

regrs1, regrd

regrd

srl

srl

regrs1, %g0, regrd

regrd, %g0, regrd

Copy and clear upper word

Clear upper word

iprefetch

label

bn, pt

%xcc, label

Instruction prefetch,

mov

mov

mov

%y, regrd

%asrn, regrd

reg_or_imm, %asrn

rd

rd

wr

%y, regrd

%asrn, regrd

%g0, reg_or_imm, %asrn

 

ret

retl

 

jmpl

jmpl

%i7+8, %g0

%o7+8, %g0

Return from subroutine

Return from leaf subroutine

setn

value, r1, r2

for -xarch=v9 same as setx value r1, r2

for -xarch=v8 same as set value r2

 

setnhi

value, r1, r2

for -xarch=v9 same as setxhi value r1, r2

for -xarch=v8 same as sethi value r2

 

setuw

value,regrd

sethi

or

sethi

or

%hi(value), regrd

%g0, value, regrd

%hi(value), regrd;

regrd, %lo(value), regrd

(value & 3FF16)==0

when 0 <= value <= 4095

(otherwise)

Do not use setuw in a DCTI delay slot.

setsw

value,regrd

sethi

or

sethi

sra

sethi

or

sethi

or

sra

%hi(value), regrd

%g0, value, regrd

%hi(value), regrd

regrd, %g0, regrd

%hi(value), regrd;

regrd, %lo(value), regrd

%hi(value), regrd;

regrd, %lo(value), regrd

regrd, %g0, regrd

value>=0 and (value & 3FF16)==0

-4096 <= value <= 4095

if (value<0) and ((value & 3FF)==0)

(otherwise, if value>=0)

(otherwise, if value<0)

Do not use setsw in a CTI delay slot.

setx

value, r1, r2

sethi

or

sethi

or

sllx

or

%hh(value), r1

r1, %hm(value), r1

%lm(value), r2

r2, %lo(value), r2

r1, 32, r1

r1, r2, r2

 

setxhi

value r1, r2

sethi

or

sethi

sllx

or

%hh(value), r1

r1, %hm(value), r1

%lm(value), r2

r1, 32, r1

r1, r2, r2

 

signx

signx

regrsl, regrd

regrd

sra

sra

regrsl, %g0, regrd

regrd, %g0, regrd

Sign-extend 32-bit value to 64 bits

 
 
 
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