SPARC-V9 Instruction Set
This appendix describes changes made to the SPARC instruction set due to the SPARC-V9 architecture. Application software for the 32-bit SPARC-V8 (Version8) architecture can execute, unchanged, on SPARC-V9 systems.
This appendix is organized into the following sections:
E.1 SPARC-V9 Changes
The SPARC-V9 architecture differs from SPARC-V8 architecture in the following areas, expanded below: registers, alternate space access, byte order, and instruction set.
These registers have been deleted:
Processor State Register
Trap Base Register
Window Invalid Mask
These registers have been widened from 32 to 64 bits:
All state registers
FSR, PC, nPC, and Y
Note - FSR Floating-Point State Register: fcc1, fcc2, and fcc3 (added floating-point condition code) bits are added and the register widened to 64-bits.
These SPARC-V9 registers are within a SPARC-V8 register field:
Condition Codes Register
Current Window Pointer
Processor Interrupt Level
Trap Base Address
These are registers that have been added.
Address Space Identifier
Floating-point Register State
Hardware clock tick-counter
Trap Next Program Counter
Trap Program Counter
Also, there are sixteen additional double-precision floating-point registers, f .. f. These registers overlap (and are aliased with) eight additional quad-precision floating-point registers, f .. f
The SPARC-V9, CWP register is decremented during a RESTORE instruction, and incremented during a SAVE instruction. This is the opposite of PSR.CWP's behavior in SPARC-V8. This change has no effect on nonprivileged instructions.
E.1.2 Alternate Space Access
Load- and store-alternate instructions to one-half of the alternate spaces can now be included in user code. In SPARC-V9, loads and stores to ASIs 0016 .. 7f16 are privileged; those to ASIs 8016 .. FF16 are nonprivileged. In SPARC-V8, access to alternate address spaces is privileged.
E.1.3 Byte Order
SPARC-V9 supports both little- and big-endian byte orders for data accesses only; instruction accesses are always performed using big-endian byte order. In SPARC-V8, all data and instruction accesses are performed in big-endian byte order.
E.2 SPARC-V9 Instruction Set Changes
Application software written for the SPARC-V8 processor runs unchanged on a SPARC-V9 processor.
E.2.1 Extended Instruction Definitions to Support the 64-bit Model
Floating-Point Compare--can set any of the four floating-point condition codes.
Load/Store FSR- only affect low-order 32 bits of FSR
Same as LD, LDA in SPARC-V8
Read/Write State Registers - access additional registers
SRA, SRL, SLL, Shifts
Split into 32-bit and 64-bit versions
(was Ticc) Operates with either the 32-bit integer condition codes (icc), or the 64-bit integer condition codes (xcc)
All other arithmetic operations operate on 64-bit operands and produce 64-bit results.
E.2.2 Added Instructions to Support 64 bits
Convert floating point to 64-bit word
Convert 64-bit word to floating point
Floating-Point Move, double and quad
Floating-point Negate, double and quad
Floating-point Absolute Value, double and quad
LDDFA, STDFA, LDFA, STFA
Alternate address space forms of LDDF, STDF, LDF, and STF
Load a signed word
Load a signed word from an alternate space
Load an extended word
Load an extended word from an alternate space
Load all 64 bits of the FSR register
Store an extended word
Store an extended word into an alternate space
Store all 64 bits if the FSR register
E.2.3 Added Instructions to Support High-Performance System Implementation
Branch on integer condition code with prediction
Branch on integer register contents with prediction
Compare and Swap from an alternate space
Branch on floating-point condition code with prediction
Move floating-point register if condition code is satisfied
Move floating-point register if integer register satisfies condition
Load/Store Quad Floating-point (in an alternate space)
Move integer register if condition code is satisfied
Move integer register if register contents satisfy condition
Generic 64-bit multiply
Signed and Unsigned 64-bit divide